As electronics become smaller and more sophisticated, devices using smaller and smaller architectures have become more desirable. In particular, research into the shrinkage of various types of memory devices is continuously being undertaken. However, certain problems exist with current technologies. Some of these problems include the non-scalability of tunnel oxides, short channel effects, and other voltage threshold variations. Scaling may result in a decrease of the charge retention time, a decrease of the coupling ratio, or increased leakage between cells in the same column. In addition, complicated design schemes to shrink the memory architecture also increase the manufacturing difficulty and cost.